
CY28551-3
....................Document #: 001-05677 Rev. *D Page 26 of 28
The following diagrams show the test load configuration for the differential CPU and PCIEX outputs.
22
M e asurem en t
Po in t
2 pF
50
22
M e asurem en t
Po in t
2 pF
50
L 1
L 2
L 1
L 2
L 1 = 0.5" , L 2 = 7 "
OU T +
OU T -
Figure 14. Differential Load Configuration for 0.7 Push Pull Clock
CP UT _ K 8
TPC B
CP UC_ K 8
15 O h m
39 00 pF
L1
L2
L3
L1
L2
L3
T PC B
39 00 pF
1 69 O h m
M e a s ur em en t
Po i n t
M e as ur em en t
Po i n t
5 pF
5 p F
12 5 O h m
1. 25V
1. 2 5 V
12 5 O h m
Figure 15. Differential Load Configuration for 3.3 Push Pull Clock
Figure 16. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)